MII(Communication)

1. About MII

Before understanding communication, it is first necessary to know what is MAC and PHY.
  MAC(Media Access Control) refers to controlling to reduce interference or collision between terminals when multiple devices share and use one medium(communication line). In other words, it controls the access right to the medium and the right to transmit data, and corresponds to the data link, which is the second layer in OSI(Open Systems Interconnection).
  PHY(Physical layer) refers to layer 1 in OSI, and is located between the transmission medium and layer 2 of OSI to transmit and receive data. Naturally, the PHY must be changed according to the type of medium (twisted pair, coaxial cable, optical fiber, air (radio wave), etc.), and the range of operating speeds(10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, etc.) is also different, so check if it is compatible with MAC.

 

The communication standard designated by the IEEE 802.3u standard to connect the MAC and PHY for 100 Mbps in 1995 by extending the existing 10 Mbps Ethernet standard is called MII(Media Independent Interface). As the name suggests, it is widely used in any environment because it can be used with any medium.
  The 16 lines for MII, which support 100 Mbps in this basic type, are spatially burdensome. For this reason, RMII (Reduced Media Independent Interface), which doubles the communication speed and cuts the number of lines in half, is also often used, so let's take a look at it together.
  For reference, communication that needs to be changed according to the medium, such as twisted pair, is called MDI(Media Dependent Interface).

 

2. MII/RMII Wiring Diagram and Packets

The MII has four data lines each for transmit and receive, and uses a reference clock of 25 MHz to match the standard 100 Mbps. In the case of RMII, it has two data lines for transmission and reception, and communicates at 100 Mbps using a reference clock of 50 MHz. Both can be changed to 10 Mbps communication. MII lowers the reference clock to 1/10 to 2.5 MHz (2.5M×4＝10M), and RMII maintains data for 10 clocks (100M÷10＝10M). It works. The wiring diagram for this is as follows.

 

 

As shown in the figure, 16 lines are connected and divided into transmission and reception. When MAC transmits, the MAC controls TX_EN(Enable) for enabling transmission and sends it through 4 transmission lines according to the TX_CLK sent by the PHY. TX_ER(Error) prevents the PHY from transmitting to the outside because the data frame being transmitted is broken when an error occurs during transmission. However, there are many cases where the line itself is not connected because it is not used well in practice, and there are cases where the PHY manufacturer does not provide it. When not in use, pull-down is recommended on the PHY side.
  When MAC receives, the PHY receives through 4 receiving lines according to RX_CLK along with RX_DV(Data Valid) indicating that the received data is valid. RX_ER informs that decoding (conversion) of a signal received from the medium into valid data is impossible.
  The remaining COL(Collision detect) and CRS(Carrier sense) are asynchronous signals independent of the clock and deliver the status detected by the PHY to the MAC during half-duplex communication. In the case of COL, it operates as ‘1’ when transmission and reception occur at the same time in half-duplex communication mode. CRS operates as '1' when it detects a carrier wave in the medium, that is, when it is transmitting or receiving. It is always ‘0’ when both are full-duplex communication. Including COL and CRS, the total number of lines is 16.
  For reference, connect an oscillator such as a crystal at 25 MHz outside of the PHY. And, when transmitting and receiving, it takes the clock as it is and outputs it through TX_CLK and RX_CLK.

 

 

As shown in the figure, RMII greatly reduced the lines in MII. In the case of transmission, TX_ER, which is not practical, is eliminated and the transmission line is cut in half at the same time. In the case of reception, CRS and RX_DV are combined to receive a composite signal called CRS_DV, removing COL and reducing the receiving line by half. And the TX_CLK of transmission and RX_CLK of reception are combined to use the transmission/reception common clock as REF_CLK (Reference: reference). This makes the number of lines 8.
  As with MII, it is common to receive 25 MHz and internally change it to 50 MHz and write it to CLK, but only for RMII, it is also directly connected to REF_CLK from the outside without going through PHY. However, note that the external wiring method does not work when the line is for output only depending on the product.

 

 

Check the picture knowing that MII recognizes data based on the rising edge of the clock for both transmit and receive. In transmission, to transmit data through twisted pair(MDI) as a medium according to TX_EN, encoding(constant conversion time required) from line to packet is required. During conversion, ‘J/K’ for the start of a packet and ‘T/R’ for ending the packet are in accordance with the 4-bit to 5-bit encoding standards and are not covered here.
  For reference, since data operating in a twisted pair is a 5-bit unit based on 25 MHz, it can be said to be 125 Mbps.

 

 

Reception should be the start of the packet based on the ‘J/K’ of the line, but depending on the decoding time from 5-bit to 4-bit, the response is delayed from RX_CRS, and RX_DV starts from the time when data is decoded. RX_CRS is delayed by that much even based on ‘T/R’, which notifies the end of the packet. (RX_CLK omitted)

 

3. Control of PHY for MII/RMII

 

Additional communication between MAC and PHY is added to specify the negotiation method(automatic or fixed), speed(10 Mbps or 100 Mbps), duplex mode(full or half duplex), and LED operation method of the connector during setting for external MDI, this is called SMI (Serial Management Interface) or MIIM (MII Management: MII Management). Although such a name exists, it is more often used as the name of the line, MDIO (Management Data Input/Output: Management Data Input/Output), rather than the communication name.
  For reference, since MDIO and MDC(Management Data Clock) can be connected in parallel similar to I2C communication, one MAC can control multiple PHYs. Also, SMI is included in PHYs for faster communication such as 1 Gbps and 10 Gbps, so make sure not to leave it out.

 

The wiring of SMI is similar to I2C communication, but the data frame is different, each frame is composed of 32-bit. The MAC sends 16-bits with the clock, including the PHY's address, write or read identifier. After that, for 16 clocks, if it is a write, the MAC transmits data, and if it is a read, the PHY responds. The clock used here is generally at a frequency of 25 MHz.

 

4. Higher level communication of MII/RMII

MII and RMII are dedicated to 10 Mbps or 100 Mbps, and for higher speeds, the number of lines and the frequency of the clock are further increased to enable communication of 1 Gbps.

 

 

In MII, the number of transmission and reception lines is changed from 4 to 8, and the clock frequency is set to 125 MHz and adjusted to 1 Gbps(125M × 8 ＝ 1G) is called GMII(Gigabit Media Independent Interface).
  For transmission, separate GTX_CLK(Gigabit Transmit) for 125 MHz and TX_CLK for 25 MHz and 2.5 MHz to support lower speeds of 100 Mbps and 10 Mbps. The point to check is that in the case of TX_CLK, the PHY generates and transmits it to the MAC, but in the case of GTX_CLK, the MAC transmits it with 8 data. This means that the PHY tries to eliminate the phase delay between sending a clock and receiving data from the MAC, and that the length of the clock and the line must be matched from GMII in terms of hardware.

In the case of reception, only the number of lines is changed from 4 to 8, and in RX_CLK, it is changed to 2.5 MHz, 25 MHz, and 125 MHz according to the communication speed. This brings the total number of lines to 25.

The clock must have an oscillation element on the outside of each MAC and PHY side, and it is still based on 25 MHz, but increases the speed internally to generate 125 MHz.

Other hardware aspects are the same as MII. Also, the standard for recognizing data is sampled at the rising edge in the same way for both transmission and reception.

 

 

Although the number of transmission and reception lines has been reduced from 8 to 4 from GMII, the clock frequency is still used at 125 MHz, but DDR(Double Data Rate, the other says ‘Double Data Transition’ or ‘Double Pumping’) uses both rising and falling edges as the standard for data recognition, and then transition applied to 1 Gbps(125M×2×4＝1G) is called RGMII (Reduced Gigabit Media Independent Interface).
  In the case of transmission, the clock is integrated into TX_CLK, and the MAC transmits it along with 4 data lines and TX_CTL(Control). TX_CTL is the sum of the TX_EN and TX_ER signals, and is sometimes denoted as TX_C, so do not confuse it with the clock.
  In the case of reception, the clock is used as it is RX_CLK, and the PHY transmits it along with 4 data lines and RX_CTL. RX_CTL is the sum of RX_DV and RX_ER signals, and is sometimes expressed as RX_C, so do not confuse it with the clock. Thus, the number of lines is reduced to 14.
  For reference, note that the operating voltage may be different depending on the version, such as 2.5 V in v1.3 and 1.5V in v2 in the case of RGMII.

 

 

Comparing GMII and RGMII as shown in the figure, it is easy to understand the characteristics of the DDR method. In the case of GMII, the clock received from the MAC through GTX_CLK is used as it is in the PHY. The PHY reads the data on the rising edge because the MAC switched it on the falling edge.
  In the case of RGMII, the PHY delays the clock received through TX_CLK from the MAC by 1/4 cycle. Since the data is switched on every edge by the MAC, the PHY reads the data on every edge with a clock delayed by 1/4 cycle. This method is called the DDR.

 

Next, in GMII, the transmission and reception lines were changed to 32 each, and the clock frequency is changed to 156.25 MHz and the DDR method was applied to fit 10 Gbps(156.25M×2×32＝10G) XGMII(10-Gigabit Media Independent Interface). In the case of XGMII, there are data lines called RX_D[31:0] and TX_D[31:0] and each four control lines called RX_C[3:0] and TX_C[3:0].
  Again, there is 25GMII(25-Gigabit Media Independent Interface), which is set to 25 Gbps(390.625M×64＝25G) by changing the transmission/reception lines to 64 each in XGMII and applying a clock frequency of 390.625 MHz. There is also 50GMII (50-Gigabit Media Independent Interface) adapted to 50 Gbps(390.625M×2×64＝50G) by applying the DDR method to 25GMII. 25GMII and 50GMII have RX_D[63:0], TX_D[63:0] data lines and 8 control lines called RX_C[7:0], TX_C[7:0].
  Details of the above-described 10 Gbps or higher communications will be omitted. In addition, communications that are faster than these communications continue to be developed and standardized.

 

5. Modification of GMII

 

When 1 Gbps is reached, since the number of lines is already excessive and the space constraint increases, transmission and reception are transformed into a serial method, which is called SGMII (Serial Gigabit Media Independent Interface). To do this, each line must reach 1 Gbps, but since it is sensitive to external influences, it is changed to a differential method to remove noise. Each inside of MAC and PHY operates at 625 MHz and reads received data in DDR method. However, the transmitted data must be decoded from 10-bit to 8-bit even when it is recognized that 8-bit is encoded as 10-bit rather than original data. In this way, only one pair of each of the transmit with transmit clocks and one pair of each of the receive with receive clocks are each adjusted to 1 Gbps(625M×2×0.8＝1G). That is, the maximum number of lines is 8, and since it can be read with an internal clock, it can be at least 4. For reference, since 10-bit per 8-bit is transmitted over the line, it can be said to be 1.25 Gbps, which is 1.25 times 1 Gbps.

In addition, there is communication that combines 4 sets of SGMII transmission rate of 1.25 Gbps from 4 PHYs, operates at 5 Gbps (625M×2×4=5G) speed of one transmitting pair and one receiving pair, and decoding in one MAC. This is called QSGMII (Quad Serial Gigabit Media Independent Interface). It is not the same, but it is easy to understand if you think of it as an ethernet switch (router) that bundles 4 ethernet ports and transmits them to one port.

 

6. Conclusion

As communication is essential in high-speed Ethernet, it is necessary to know it, and it is good to know the MDI, which is the communication section after the PHY, as well.