MII(Communication)

1. About MII

Before understanding communication, it is first necessary to know what is MAC and PHY.
  MAC(Media Access Control) refers to controlling to reduce interference or collision between terminals when multiple devices share and use one medium(communication line). In other words, it controls the access right to the medium and the right to transmit data, and corresponds to the data link, which is the second layer in OSI(Open Systems Interconnection).
  PHY(Physical layer) refers to layer 1 in OSI, and is located between the transmission medium and layer 2 of OSI to transmit and receive data. Naturally, the PHY must be changed according to the type of medium (twisted pair, coaxial cable, optical fiber, air (radio wave), etc.), and the range of operating speeds(10 Mbps, 100 Mbps, 1 Gbps, 10 Gbps, etc.) is also different, so check if it is compatible with MAC.

 

The communication standard designated by the IEEE 802.3u standard to connect the MAC and PHY for 100 Mbps in 1995 by extending the existing 10 Mbps Ethernet standard is called MII(Media Independent Interface). As the name suggests, it is widely used in any environment because it can be used with any medium.
  The 16 lines for MII, which support 100 Mbps in this basic type, are spatially burdensome. For this reason, RMII (Reduced Media Independent Interface), which doubles the communication speed and cuts the number of lines in half, is also often used, so let's take a look at it together.
  For reference, communication that needs to be changed according to the medium, such as twisted pair, is called MDI(Media Dependent Interface).

 

2. MII/RMII Wiring Diagram and Packets

The MII has four data lines each for transmit and receive, and uses a reference clock of 25 MHz to match the standard 100 Mbps. In the case of RMII, it has two data lines for transmission and reception, and communicates at 100 Mbps using a reference clock of 50 MHz. Both can be changed to 10 Mbps communication. MII lowers the reference clock to 1/10 to 2.5 MHz (2.5M×4＝10M), and RMII maintains data for 10 clocks (100M÷10＝10M). It works. The wiring diagram for this is as follows.

 

 

As shown in the figure, 16 lines are connected and divided into transmission and reception. When MAC transmits, the MAC controls TX_EN(Enable) for enabling transmission and sends it through 4 transmission lines according to the TX_CLK sent by the PHY. TX_ER(Error) prevents the PHY from transmitting to the outside because the data frame being transmitted is broken when an error occurs during transmission. However, there are many cases where the line itself is not connected because it is not used well in practice, and there are cases where the PHY manufacturer does not provide it. When not in use, pull-down is recommended on the PHY side.
  When MAC receives, the PHY receives through 4 receiving lines according to RX_CLK along with RX_DV(Data Valid) indicating that the received data is valid. RX_ER informs that decoding (conversion) of a signal received from the medium into valid data is impossible.
  The remaining COL(Collision detect) and CRS(Carrier sense) are asynchronous signals independent of the clock and deliver the status detected by the PHY to the MAC during half-duplex communication. In the case of COL, it operates as ‘1’ when transmission and reception occur at the same time in half-duplex communication mode. CRS operates as '1' when it detects a carrier wave in the medium, that is, when it is transmitting or receiving. It is always ‘0’ when both are full-duplex communication. Including COL and CRS, the total number of lines is 16.
  For reference, connect an oscillator such as a crystal at 25 MHz outside of the PHY. And, when transmitting and receiving, it takes the clock as it is and outputs it through TX_CLK and RX_CLK.

 

 

As shown in the figure, RMII greatly reduced the lines in MII. In the case of transmission, TX_ER, which is not practical, is eliminated and the transmission line is cut in half at the same time. In the case of reception, CRS and RX_DV are combined to receive a composite signal called CRS_DV, removing COL and reducing the receiving line by half. And the TX_CLK of transmission and RX_CLK of reception are combined to use the transmission/reception common clock as REF_CLK (Reference: reference). This makes the number of lines 8.
  As with MII, it is common to receive 25 MHz and internally change it to 50 MHz and write it to CLK, but only for RMII, it is also directly connected to REF_CLK from the outside without going through PHY. However, note that the external wiring method does not work when the line is for output only depending on the product.

 

 

Check the picture knowing that MII recognizes data based on the rising edge of the clock for both transmit and receive. In transmission, to transmit data through twisted pair(MDI) as a medium according to TX_EN, encoding(constant conversion time required) from line to packet is required. During conversion, ‘J/K’ for the start of a packet and ‘T/R’ for ending the packet are in accordance with the 4-bit to 5-bit encoding standards and are not covered here.
  For reference, since data operating in a twisted pair is a 5-bit unit based on 25 MHz, it can be said to be 125 Mbps.

 

 

Reception should be the start of the packet based on the ‘J/K’ of the line, but depending on the decoding time from 5-bit to 4-bit, the response is delayed from RX_CRS, and RX_DV starts from the time when data is decoded. RX_CRS is delayed by that much even based on ‘T/R’, which notifies the end of the packet. (RX_CLK omitted)

 

3. Control of PHY for MII/RMII

 

Additional communication between MAC and PHY is added to specify the negotiation method(automatic or fixed), speed(10 Mbps or 100 Mbps), duplex mode(full or half duplex), and LED operation method of the connector during setting for external MDI, this is called SMI (Serial Management Interface) or MIIM (MII Management: MII Management). Although such a name exists, it is more often used as the name of the line, MDIO (Management Data Input/Output: Management Data Input/Output), rather than the communication name.
  For reference, since MDIO and MDC(Management Data Clock) can be connected in parallel similar to I2C communication, one MAC can control multiple PHYs. Also, SMI is included in PHYs for faster communication such as 1 Gbps and 10 Gbps, so make sure not to leave it out.

 

The wiring of SMI is similar to I2C communication, but the data frame is different, each frame is composed of 32-bit. The MAC sends 16-bits with the clock, including the PHY's address, write or read identifier. After that, for 16 clocks, if it is a write, the MAC transmits data, and if it is a read, the PHY responds. The clock used here is generally at a frequency of 25 MHz.

 

4. Higher level communication of MII/RMII

MII and RMII are dedicated to 10 Mbps or 100 Mbps, and for higher speeds, the number of lines and the frequency of the clock are further increased to enable communication of 1 Gbps.

 

 

In MII, the number of transmission and reception lines is changed from 4 to 8, and the clock frequency is set to 125 MHz and adjusted to 1 Gbps(125M × 8 ＝ 1G) is called GMII(Gigabit Media Independent Interface).
  For transmission, separate GTX_CLK(Gigabit Transmit) for 125 MHz and TX_CLK for 25 MHz and 2.5 MHz to support lower speeds of 100 Mbps and 10 Mbps. The point to check is that in the case of TX_CLK, the PHY generates and transmits it to the MAC, but in the case of GTX_CLK, the MAC transmits it with 8 data. This means that the PHY tries to eliminate the phase delay between sending a clock and receiving data from the MAC, and that the length of the clock and the line must be matched from GMII in terms of hardware.

In the case of reception, only the number of lines is changed from 4 to 8, and in RX_CLK, it is changed to 2.5 MHz, 25 MHz, and 125 MHz according to the communication speed. This brings the total number of lines to 25.

The clock must have an oscillation element on the outside of each MAC and PHY side, and it is still based on 25 MHz, but increases the speed internally to generate 125 MHz.

Other hardware aspects are the same as MII. Also, the standard for recognizing data is sampled at the rising edge in the same way for both transmission and reception.

 

 

Although the number of transmission and reception lines has been reduced from 8 to 4 from GMII, the clock frequency is still used at 125 MHz, but DDR(Double Data Rate, the other says ‘Double Data Transition’ or ‘Double Pumping’) uses both rising and falling edges as the standard for data recognition, and then transition applied to 1 Gbps(125M×2×4＝1G) is called RGMII (Reduced Gigabit Media Independent Interface).
  In the case of transmission, the clock is integrated into TX_CLK, and the MAC transmits it along with 4 data lines and TX_CTL(Control). TX_CTL is the sum of the TX_EN and TX_ER signals, and is sometimes denoted as TX_C, so do not confuse it with the clock.
  In the case of reception, the clock is used as it is RX_CLK, and the PHY transmits it along with 4 data lines and RX_CTL. RX_CTL is the sum of RX_DV and RX_ER signals, and is sometimes expressed as RX_C, so do not confuse it with the clock. Thus, the number of lines is reduced to 14.
  For reference, note that the operating voltage may be different depending on the version, such as 2.5 V in v1.3 and 1.5V in v2 in the case of RGMII.

 

 

Comparing GMII and RGMII as shown in the figure, it is easy to understand the characteristics of the DDR method. In the case of GMII, the clock received from the MAC through GTX_CLK is used as it is in the PHY. The PHY reads the data on the rising edge because the MAC switched it on the falling edge.
  In the case of RGMII, the PHY delays the clock received through TX_CLK from the MAC by 1/4 cycle. Since the data is switched on every edge by the MAC, the PHY reads the data on every edge with a clock delayed by 1/4 cycle. This method is called the DDR.

 

Next, in GMII, the transmission and reception lines were changed to 32 each, and the clock frequency is changed to 156.25 MHz and the DDR method was applied to fit 10 Gbps(156.25M×2×32＝10G) XGMII(10-Gigabit Media Independent Interface). In the case of XGMII, there are data lines called RX_D[31:0] and TX_D[31:0] and each four control lines called RX_C[3:0] and TX_C[3:0].
  Again, there is 25GMII(25-Gigabit Media Independent Interface), which is set to 25 Gbps(390.625M×64＝25G) by changing the transmission/reception lines to 64 each in XGMII and applying a clock frequency of 390.625 MHz. There is also 50GMII (50-Gigabit Media Independent Interface) adapted to 50 Gbps(390.625M×2×64＝50G) by applying the DDR method to 25GMII. 25GMII and 50GMII have RX_D[63:0], TX_D[63:0] data lines and 8 control lines called RX_C[7:0], TX_C[7:0].
  Details of the above-described 10 Gbps or higher communications will be omitted. In addition, communications that are faster than these communications continue to be developed and standardized.

 

5. Modification of GMII

 

When 1 Gbps is reached, since the number of lines is already excessive and the space constraint increases, transmission and reception are transformed into a serial method, which is called SGMII (Serial Gigabit Media Independent Interface). To do this, each line must reach 1 Gbps, but since it is sensitive to external influences, it is changed to a differential method to remove noise. Each inside of MAC and PHY operates at 625 MHz and reads received data in DDR method. However, the transmitted data must be decoded from 10-bit to 8-bit even when it is recognized that 8-bit is encoded as 10-bit rather than original data. In this way, only one pair of each of the transmit with transmit clocks and one pair of each of the receive with receive clocks are each adjusted to 1 Gbps(625M×2×0.8＝1G). That is, the maximum number of lines is 8, and since it can be read with an internal clock, it can be at least 4. For reference, since 10-bit per 8-bit is transmitted over the line, it can be said to be 1.25 Gbps, which is 1.25 times 1 Gbps.

In addition, there is communication that combines 4 sets of SGMII transmission rate of 1.25 Gbps from 4 PHYs, operates at 5 Gbps (625M×2×4=5G) speed of one transmitting pair and one receiving pair, and decoding in one MAC. This is called QSGMII (Quad Serial Gigabit Media Independent Interface). It is not the same, but it is easy to understand if you think of it as an ethernet switch (router) that bundles 4 ethernet ports and transmits them to one port.

 

6. Conclusion

As communication is essential in high-speed Ethernet, it is necessary to know it, and it is good to know the MDI, which is the communication section after the PHY, as well.

 

I2C Communication

1. About I²C communication

Serial communication USART, which was basically used, is only used 1:1. Therefore, in order to connect with multiple devices, multiple transceivers corresponding thereto are required, so there is a limitation in hardware. To improve this, communication was developed by Philips in the 1980s to tie transmit and receive and branch off this and another clock line to connect another device. It is called I²C ([eye-squared-C] or IIC, Inter -Integrated Circuit). Let's learn about this I²C communication.

 

2. I²C communication wiring diagram

 

As shown in the figure, the I²C wiring diagram connects SCL (Serial Clock) and SDA (Serial Data) and adds a pull-up resistor to both lines. And the device that manages the clock and transmits it together with the clock is Controller, and the device that receives the clock and responds to the data is the Target. In addition, it is a synchronous half-duplex communication that transmits and receives on one line.
  Since both SCL and SDA outputs are open-collector or open-drain, an external pull-up resistor is absolutely necessary. However, rather than calculating this resistance value, the general values of 2.2 kΩ, 3.3 kΩ, and 4.7 kΩ are appropriately determined. decide There are several modes for speed, so use it according to the mode supported by the target device.

 

 

Add Target to change communication from 1：1 to 1：N as shown in the figure. Even when there are two Targets, the two lines are branched and connected in the same way, but there is no additional resistor added. By increasing the number of Targets to 3 or more, up to 127 (7-bit address method) or 1023 (10-bit address method) is possible. However, if there are many branched lines, it may be necessary to adjust the value of the resistor due to the capacitance problem on the line.
  For reference, I²C communication is an N：N method, and there are cases where there are two or more control devices, but it is a method of controlling by determining the status of clock and data to take priority of control. When dividing into Controller 1 and Controller 2, Controller 2 waits while Controller 1 transmits data and takes control when the end of data transmission is confirmed.

 

3. Operation mode of I²C communication

According to the supported speed, it is divided into 5 names and used. If the Target supports a certain mode, it means that it operates at a speed lower than that, but since the data frame of I2C communication is quite long, it is mostly possible to use the maximum speed possible.

 

Operation Mode	Max. Speed	Max. Capacitance	Max. Rise/Fall Time
Low-speed mode(Ls)	10 kbps	-	-
Standard mode(Sm)	100 kbps	400 pF	1000 ns / 300 ns
Fast mode(Fm)	400 kbps	400 pF	300 ns / 300 ns
Fast mode+(Fm+)	1 Mbps	550 pF	120 ns / 120 ns
High-speed mode(Hs)	1.7 Mbps	400 pF	80 ns / 80 ns
High-speed mode(Hs)	3.4 Mbps	100 pF	40 ns / 40 ns

 

First of all, the Low-speed mode is known as a standard for compatibility with other communications, and is not an officially used operation mode in I2C communications. And, the High-speed mode is divided into two by the capacitance on the line, and you can think of it as operating up to 1.7 Mbps at a maximum of 400 pF and 3.4 Mbps at a maximum of 100 pF. In addition to these, there is a communication called Ultra-fast mode(UFm) of 5 Mbps, but since it is a push-pull type one-way communication(write only), it is treated separately here.

 

4. I²C communication data frame

 

As shown in the figure, in the inactive state before the data frame, both lines maintain a high level according to the pull-up resistor. Then, at the beginning, the control device changes the SDA line to a low level and informs the target device of the start of the frame. This is called the Start Condition. Conversely, when SCL is high at the end, SDA changes to high level is called a stop condition. These start and stop conditions indicate the start and end of a data frame, and in the case of multiple Controller, it becomes the standard for exchanging authority to control.
Next, when looking at the structure, after the start condition, the control device transmits 8-bits by adding read (‘1’) or write (‘0’) together with the 7-bit address of the target device. Immediately after, the Target corresponding to the address changes to a low level and informs the Controller that it is ready. This is called ACK(Acknowledgment). If the Target cannot respond, it is maintained at a high level by pull-up, which is called NACK(Not-acknowledgement). When the ACK is confirmed, the Controller transmits data, and when NACK is confirmed, the Controller determines that there is no Target to respond and ends the communication.
  If you look at only the address, it is divided into the upper 4 digits(A6 to A3) and the lower 3 digits(A2 to A0)＋R/W’. Most of them are designated by the manufacturer except for the special commands in the case of 0000 and 1111 in the upper 4 digits. And the lower 3 digits are provided so that it can be slightly changed due to hardware design. Accordingly, a plurality of Target of the same type may be connected within the same line. The R/W' bit becomes R/W’＝1 when the Controller wants to receive(read) the subsequent command, and R/W’＝0 when it wants to transmit(write).

 

 

The figure is a data frame where R/W’＝1 and writing is executed. When the response is ACK by sending the Target address, the Controller transmits the internal address to execute write again. At this time, every 8-bit transmission must receive an ACK, and then send the data to be written. The ACK is checked until the last data, and the frame is terminated at the judgment of the Controller. This sequence is illustrated in the figure below.

 

 

In the case of read, if R/W’＝1 is transmitted, the data is received immediately after confirmation of the ACK, so the internal address to be read cannot be determined. Therefore, in advance, R/W’ ＝0 is written and the internal address is designated but data is not transmitted. After that, R/W’ ＝1 is transmitted, the data of the Target is read, and again, the Controller replies with an ACK every 8-bit. The data frame ends with the response after the Controller read to the end as NACK.

These processes are different for each target device, so check and change accordingly.

 

 

The 10-bit address is divided into two bytes and transmitted from the Controller as shown in the figure. For the first A14~A10, it informs the device on the line that it is a 10-bit address method with ‘11110’, and transmits the remaining addresses A9~A8 and R/W’ to receive a response from the corresponding Target. Then, the Target is specified by transmitting A7 to A0. After that, the part that designates the internal address of the Target is the same.

 

5. SMBus communication, PMBus communication

A derivative of I²C defined by Intel and Duracell in the 1990s for communication with power-related devices such as the rechargeable battery system of a motherboard in a laptop is called SMBus(System Management Bus). SMBus continued to be used as communication for controlling smart battery system (SBS), and in the 2000s, several companies improved it based on SMBus again for power system management, which is called PMBus(Power Management Bus).

 

	I2C	SMBus	PMBus
Speed range	0 ~ 3.4 Mbps(Bi-dir)	10 ~ 100 kbps(v2.0)	10 ~ 400 kbps
	0 ~ 5 Mbps(Uni-dir)	10 ~ 1 Mbps(v3.0)
Clock Timeout	No	Yes	Yes
Address length	7 bit(127)/10 bit(1023)	7 bit(128)	7 bit(128)
Limit on frame	No	32 Byte	255 Byte
Sink current	3 mA Max.	350 uA Max.(v1.1)	350 uA Max.(v1.0)
		4 mA Max.(v2.0)
Low level reference voltage	0.3×VDD V	0.8 V	0.8 V
High level reference voltage	0.7×VDD V	2.1 V	2.1 V
Error check	No	PEC(v1.1, CRC-8)	PEC(v1.0, CRC-8)

 

Both SMBus and PMBus are variants of I²C, and although the wiring method is half-duplex communication with two lines, clock and data, there are some differences in detail, which may not be compatible depending on the wiring environment. Due to the time limit, the minimum operating speed is determined and the range of the driving current is different, so it may be necessary to modify the pull-up resistor. In addition, refer to the fact that PEC(Packet Error Checking) is included in the communication frame itself.

 

6. Conclusion

I²C should be reviewed when slow but multi-connected serial communication is required, such as PROM-type memory, input/output expander, and thermo/hygrometer.

SPI Communication

1. About SPI communication

Serial communication USART, which was basically used, is only used 1：1. Therefore, in order to connect with multiple devices, multiple transceivers corresponding thereto are required, so there is a limitation in hardware. To improve this, communication that connects another device by branching off each line of transmit, receive, and clock was developed by Motorola in the 1980s, which is called SPI (Serial Peripheral Interface). Learn about this SPI communication.

 

2. SPI communication wiring diagram

 

As shown in the figure, the wiring diagram of SPI communication connects between MOSI (Master Out, Slave In), MISO (Master In, Slave Out), SCLK (Serial Clock), and SS# (Slave Select). It is a synchronous full-duplex communication in which the direction of transmission or reception for MOSI and MISO is determined depending on whether the device is a master device or a slave device.
  SS' is a low level active method, and should be maintained at a high level during normal times. SCLK is managed only by the master, and data is transmitted to MOSI along with the clock. Slave transmits to MISO according to the received clock. The communication speed is not set, but it operates only if it is set within the upper limit of the operation of the slave device. Usually, the range is wide from 1 Mbps to over 50 Mbps.

 

 

Add a slave to change communication from 1：1 to 1：N as shown in the figure. When there are two slave devices, a line connecting the master to SS₂# is added, and a low level signal is given to SS₁# when communicating with first slave and to SS₂# when communicating with second slave to determine the communication target. When the third generation is added, SS₃# added from the master is connected with the SS# of the slave. If you continue to add in the same way, there is no limit on the number of communication itself, but there is a limit on the number of individual lines for the master to control SS#. Therefore, instead of reducing the number of SS# lines, there is also a daisy-chain wiring method in which the master's command and the slave's response must be made in order, but it is omitted here.

 

3. Operation mode of SPI communication

 

Unlike other communications, SPI communication has to set the time to recognize data based on the clock. As shown in the figure, the center of each data is the standard for the sampling position to read two values. At this time, it depends on whether the edge of the clock is the first or the second, and whether the phase of the clock is normal or inverted. For CLK0 and CLK1, both are in normal phase, but CLK0 is read from the first edge and CLK1 is read from the second edge. CLK2 and CLK3 are in inverted phase, CLK2 is read from the first edge and CLK3 is read from the second edge. In this way, communication is possible only when the master and slave select one of the four options as the SPI mode. The four modes are summarized as follows.

 

SPI Mode	Phase Inversion(CPOL)	Phase Delay(CPHA)
0	Normal(0)	Immediate(0)
1	Normal(0)	Delay(1)
2	Invert(1)	Immediate(0)
3	Invert(1)	Delay(1)

 

Comparing with the figure above, the normal phase is CPOL(Clock Polarity)＝0 based on the clock, the inverted phase is CPOL＝1, the first edge of the sampling reference is CPHA (Clock Phase)＝0, and the second edge is CPHA＝1. can see. It is recommended to check the waveform and mode number as each manufacturer may differ from the expression method in the table.

 

4. SPI communication data frame

 

In SPI communication, there is virtually no fixed data frame. Because the amount of data bits is not determined as the active state and the inactive state are divided by the level of SS#, and the data frame transmitted and received from the falling edge of the signal to the rising edge. As shown in the figure, only the clock(SPI Mode 0) in the active state is regarded as data, and nothing else is recognized. Depending on the connected device, it may be ‘0’ or ‘1’ in the idle state, but all will be ignored.
  The figure shows that MSB(Most Significant Bit) is transmitted for 8 bits, but if necessary, it can be changed to LSB(Least Significant Bit) first. In addition, a larger amount of transmission is possible depending on the length of SS#, and it is also possible to process one frame that is usually from 8 bits to more than 100 bits as long.
  For reference, when comparing 100 communication with 8 bits and communication with 800 bits once, it takes longer to repeat frame-by-frame transmission even if the amount of data is the same. This is because, whenever a transmission is transmitted, the delay due to the transition and the time in the idle state are also accumulated. Therefore, it is advantageous to send as much as possible at once, but in some cases, it is difficult for the receiver to process too much data, so the size of the data frame should be decided in consideration of the communication cycle and the surrounding environment. The following is an example of 16-bit continuous transmission.

 

5. DSPI, QSPI communication

 

Like the structure in which the slave responds after the master makes a request during SPI communication, there is a hardware that has been changed to enable transmission and reception of both lines on the premise that transmission and reception do not occur at the same time. This is called DSPI(Dual Serial Peripheral Interface: Dual SPI), and it doubles both transmission and reception speed with two half-duplex circuits. If MOSI becomes IO0 and takes care of even bits, and MISO becomes IO1 and takes charge of odd bits, it is possible to transmit 1 byte at the 4th clock.

 

 

Add IO2 and IO3 to DSPI again, IO0 takes over bits 0 and 4, IO1 takes bits 1 and 5, IO2 handles bits 2 and 6, and IO3 takes over bits 3 and 7 for transmission and reception. In this way, there is also QSPI (Quad Serial Peripheral Interface: Quadruple SPI) where one byte transfer ends at the second clock. These communications are often seen in high-speed memory circuits that require fast reads and writes.

 

6. Conclusion

When you need fast serial communication such as RAM-type memory, multi-channel ADC/DAC, or color LCD, consider SPI communication.