I2C Communication

1. About I²C communication

Serial communication USART, which was basically used, is only used 1:1. Therefore, in order to connect with multiple devices, multiple transceivers corresponding thereto are required, so there is a limitation in hardware. To improve this, communication was developed by Philips in the 1980s to tie transmit and receive and branch off this and another clock line to connect another device. It is called I²C ([eye-squared-C] or IIC, Inter -Integrated Circuit). Let's learn about this I²C communication.

 

2. I²C communication wiring diagram

 

As shown in the figure, the I²C wiring diagram connects SCL (Serial Clock) and SDA (Serial Data) and adds a pull-up resistor to both lines. And the device that manages the clock and transmits it together with the clock is Controller, and the device that receives the clock and responds to the data is the Target. In addition, it is a synchronous half-duplex communication that transmits and receives on one line.
  Since both SCL and SDA outputs are open-collector or open-drain, an external pull-up resistor is absolutely necessary. However, rather than calculating this resistance value, the general values of 2.2 kΩ, 3.3 kΩ, and 4.7 kΩ are appropriately determined. decide There are several modes for speed, so use it according to the mode supported by the target device.

 

 

Add Target to change communication from 1：1 to 1：N as shown in the figure. Even when there are two Targets, the two lines are branched and connected in the same way, but there is no additional resistor added. By increasing the number of Targets to 3 or more, up to 127 (7-bit address method) or 1023 (10-bit address method) is possible. However, if there are many branched lines, it may be necessary to adjust the value of the resistor due to the capacitance problem on the line.
  For reference, I²C communication is an N：N method, and there are cases where there are two or more control devices, but it is a method of controlling by determining the status of clock and data to take priority of control. When dividing into Controller 1 and Controller 2, Controller 2 waits while Controller 1 transmits data and takes control when the end of data transmission is confirmed.

 

3. Operation mode of I²C communication

According to the supported speed, it is divided into 5 names and used. If the Target supports a certain mode, it means that it operates at a speed lower than that, but since the data frame of I2C communication is quite long, it is mostly possible to use the maximum speed possible.

 

Operation Mode	Max. Speed	Max. Capacitance	Max. Rise/Fall Time
Low-speed mode(Ls)	10 kbps	-	-
Standard mode(Sm)	100 kbps	400 pF	1000 ns / 300 ns
Fast mode(Fm)	400 kbps	400 pF	300 ns / 300 ns
Fast mode+(Fm+)	1 Mbps	550 pF	120 ns / 120 ns
High-speed mode(Hs)	1.7 Mbps	400 pF	80 ns / 80 ns
High-speed mode(Hs)	3.4 Mbps	100 pF	40 ns / 40 ns

 

First of all, the Low-speed mode is known as a standard for compatibility with other communications, and is not an officially used operation mode in I2C communications. And, the High-speed mode is divided into two by the capacitance on the line, and you can think of it as operating up to 1.7 Mbps at a maximum of 400 pF and 3.4 Mbps at a maximum of 100 pF. In addition to these, there is a communication called Ultra-fast mode(UFm) of 5 Mbps, but since it is a push-pull type one-way communication(write only), it is treated separately here.

 

4. I²C communication data frame

 

As shown in the figure, in the inactive state before the data frame, both lines maintain a high level according to the pull-up resistor. Then, at the beginning, the control device changes the SDA line to a low level and informs the target device of the start of the frame. This is called the Start Condition. Conversely, when SCL is high at the end, SDA changes to high level is called a stop condition. These start and stop conditions indicate the start and end of a data frame, and in the case of multiple Controller, it becomes the standard for exchanging authority to control.
Next, when looking at the structure, after the start condition, the control device transmits 8-bits by adding read (‘1’) or write (‘0’) together with the 7-bit address of the target device. Immediately after, the Target corresponding to the address changes to a low level and informs the Controller that it is ready. This is called ACK(Acknowledgment). If the Target cannot respond, it is maintained at a high level by pull-up, which is called NACK(Not-acknowledgement). When the ACK is confirmed, the Controller transmits data, and when NACK is confirmed, the Controller determines that there is no Target to respond and ends the communication.
  If you look at only the address, it is divided into the upper 4 digits(A6 to A3) and the lower 3 digits(A2 to A0)＋R/W’. Most of them are designated by the manufacturer except for the special commands in the case of 0000 and 1111 in the upper 4 digits. And the lower 3 digits are provided so that it can be slightly changed due to hardware design. Accordingly, a plurality of Target of the same type may be connected within the same line. The R/W' bit becomes R/W’＝1 when the Controller wants to receive(read) the subsequent command, and R/W’＝0 when it wants to transmit(write).

 

 

The figure is a data frame where R/W’＝1 and writing is executed. When the response is ACK by sending the Target address, the Controller transmits the internal address to execute write again. At this time, every 8-bit transmission must receive an ACK, and then send the data to be written. The ACK is checked until the last data, and the frame is terminated at the judgment of the Controller. This sequence is illustrated in the figure below.

 

 

In the case of read, if R/W’＝1 is transmitted, the data is received immediately after confirmation of the ACK, so the internal address to be read cannot be determined. Therefore, in advance, R/W’ ＝0 is written and the internal address is designated but data is not transmitted. After that, R/W’ ＝1 is transmitted, the data of the Target is read, and again, the Controller replies with an ACK every 8-bit. The data frame ends with the response after the Controller read to the end as NACK.

These processes are different for each target device, so check and change accordingly.

 

 

The 10-bit address is divided into two bytes and transmitted from the Controller as shown in the figure. For the first A14~A10, it informs the device on the line that it is a 10-bit address method with ‘11110’, and transmits the remaining addresses A9~A8 and R/W’ to receive a response from the corresponding Target. Then, the Target is specified by transmitting A7 to A0. After that, the part that designates the internal address of the Target is the same.

 

5. SMBus communication, PMBus communication

A derivative of I²C defined by Intel and Duracell in the 1990s for communication with power-related devices such as the rechargeable battery system of a motherboard in a laptop is called SMBus(System Management Bus). SMBus continued to be used as communication for controlling smart battery system (SBS), and in the 2000s, several companies improved it based on SMBus again for power system management, which is called PMBus(Power Management Bus).

 

	I2C	SMBus	PMBus
Speed range	0 ~ 3.4 Mbps(Bi-dir)	10 ~ 100 kbps(v2.0)	10 ~ 400 kbps
	0 ~ 5 Mbps(Uni-dir)	10 ~ 1 Mbps(v3.0)
Clock Timeout	No	Yes	Yes
Address length	7 bit(127)/10 bit(1023)	7 bit(128)	7 bit(128)
Limit on frame	No	32 Byte	255 Byte
Sink current	3 mA Max.	350 uA Max.(v1.1)	350 uA Max.(v1.0)
		4 mA Max.(v2.0)
Low level reference voltage	0.3×VDD V	0.8 V	0.8 V
High level reference voltage	0.7×VDD V	2.1 V	2.1 V
Error check	No	PEC(v1.1, CRC-8)	PEC(v1.0, CRC-8)

 

Both SMBus and PMBus are variants of I²C, and although the wiring method is half-duplex communication with two lines, clock and data, there are some differences in detail, which may not be compatible depending on the wiring environment. Due to the time limit, the minimum operating speed is determined and the range of the driving current is different, so it may be necessary to modify the pull-up resistor. In addition, refer to the fact that PEC(Packet Error Checking) is included in the communication frame itself.

 

6. Conclusion

I²C should be reviewed when slow but multi-connected serial communication is required, such as PROM-type memory, input/output expander, and thermo/hygrometer.