SPI Communication

1. About SPI communication

Serial communication USART, which was basically used, is only used 1：1. Therefore, in order to connect with multiple devices, multiple transceivers corresponding thereto are required, so there is a limitation in hardware. To improve this, communication that connects another device by branching off each line of transmit, receive, and clock was developed by Motorola in the 1980s, which is called SPI (Serial Peripheral Interface). Learn about this SPI communication.

 

2. SPI communication wiring diagram

 

As shown in the figure, the wiring diagram of SPI communication connects between MOSI (Master Out, Slave In), MISO (Master In, Slave Out), SCLK (Serial Clock), and SS# (Slave Select). It is a synchronous full-duplex communication in which the direction of transmission or reception for MOSI and MISO is determined depending on whether the device is a master device or a slave device.
  SS' is a low level active method, and should be maintained at a high level during normal times. SCLK is managed only by the master, and data is transmitted to MOSI along with the clock. Slave transmits to MISO according to the received clock. The communication speed is not set, but it operates only if it is set within the upper limit of the operation of the slave device. Usually, the range is wide from 1 Mbps to over 50 Mbps.

 

 

Add a slave to change communication from 1：1 to 1：N as shown in the figure. When there are two slave devices, a line connecting the master to SS₂# is added, and a low level signal is given to SS₁# when communicating with first slave and to SS₂# when communicating with second slave to determine the communication target. When the third generation is added, SS₃# added from the master is connected with the SS# of the slave. If you continue to add in the same way, there is no limit on the number of communication itself, but there is a limit on the number of individual lines for the master to control SS#. Therefore, instead of reducing the number of SS# lines, there is also a daisy-chain wiring method in which the master's command and the slave's response must be made in order, but it is omitted here.

 

3. Operation mode of SPI communication

 

Unlike other communications, SPI communication has to set the time to recognize data based on the clock. As shown in the figure, the center of each data is the standard for the sampling position to read two values. At this time, it depends on whether the edge of the clock is the first or the second, and whether the phase of the clock is normal or inverted. For CLK0 and CLK1, both are in normal phase, but CLK0 is read from the first edge and CLK1 is read from the second edge. CLK2 and CLK3 are in inverted phase, CLK2 is read from the first edge and CLK3 is read from the second edge. In this way, communication is possible only when the master and slave select one of the four options as the SPI mode. The four modes are summarized as follows.

 

SPI Mode	Phase Inversion(CPOL)	Phase Delay(CPHA)
0	Normal(0)	Immediate(0)
1	Normal(0)	Delay(1)
2	Invert(1)	Immediate(0)
3	Invert(1)	Delay(1)

 

Comparing with the figure above, the normal phase is CPOL(Clock Polarity)＝0 based on the clock, the inverted phase is CPOL＝1, the first edge of the sampling reference is CPHA (Clock Phase)＝0, and the second edge is CPHA＝1. can see. It is recommended to check the waveform and mode number as each manufacturer may differ from the expression method in the table.

 

4. SPI communication data frame

 

In SPI communication, there is virtually no fixed data frame. Because the amount of data bits is not determined as the active state and the inactive state are divided by the level of SS#, and the data frame transmitted and received from the falling edge of the signal to the rising edge. As shown in the figure, only the clock(SPI Mode 0) in the active state is regarded as data, and nothing else is recognized. Depending on the connected device, it may be ‘0’ or ‘1’ in the idle state, but all will be ignored.
  The figure shows that MSB(Most Significant Bit) is transmitted for 8 bits, but if necessary, it can be changed to LSB(Least Significant Bit) first. In addition, a larger amount of transmission is possible depending on the length of SS#, and it is also possible to process one frame that is usually from 8 bits to more than 100 bits as long.
  For reference, when comparing 100 communication with 8 bits and communication with 800 bits once, it takes longer to repeat frame-by-frame transmission even if the amount of data is the same. This is because, whenever a transmission is transmitted, the delay due to the transition and the time in the idle state are also accumulated. Therefore, it is advantageous to send as much as possible at once, but in some cases, it is difficult for the receiver to process too much data, so the size of the data frame should be decided in consideration of the communication cycle and the surrounding environment. The following is an example of 16-bit continuous transmission.

 

5. DSPI, QSPI communication

 

Like the structure in which the slave responds after the master makes a request during SPI communication, there is a hardware that has been changed to enable transmission and reception of both lines on the premise that transmission and reception do not occur at the same time. This is called DSPI(Dual Serial Peripheral Interface: Dual SPI), and it doubles both transmission and reception speed with two half-duplex circuits. If MOSI becomes IO0 and takes care of even bits, and MISO becomes IO1 and takes charge of odd bits, it is possible to transmit 1 byte at the 4th clock.

 

 

Add IO2 and IO3 to DSPI again, IO0 takes over bits 0 and 4, IO1 takes bits 1 and 5, IO2 handles bits 2 and 6, and IO3 takes over bits 3 and 7 for transmission and reception. In this way, there is also QSPI (Quad Serial Peripheral Interface: Quadruple SPI) where one byte transfer ends at the second clock. These communications are often seen in high-speed memory circuits that require fast reads and writes.

 

6. Conclusion

When you need fast serial communication such as RAM-type memory, multi-channel ADC/DAC, or color LCD, consider SPI communication.